Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein

ABSTRACT

A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a microcontroller, and moreparticularly, to a micro-controller which compresses instruction codesand stores the compressed instruction codes in a program memory.

[0003] 2. Description of the Related Art

[0004] A micro-controller is a device which is incorporated in anelectric device such as electric appliances, audio-visual (AV) devices,portable telephones, cars and the like to control the device associatedtherewith by executing processes in accordance with programs stored in abuilt-in read only program memory (ROM).

[0005] The micro-controller is required to provide performance necessaryto control an associated device and to be inexpensive, from the natureof the micro-controller that is incorporated in a device forutilization.

[0006] In recent years, however, processes executed by themicro-controller have become increasingly complicated, with an increasedcapacity of a program memory required for the processes. For thisreason, the program memory accounts for an increasingly higherproportion in the micro-controller, and this trend is thought to remainunchanged in the future. Generally, since an increased capacity of theprogram memory results in a correspondingly higher cost, it is acritical problem to limit the capacity of the program memory forproviding an inexpensive micro-controller.

[0007] For general-purpose information processing apparatuses such aspersonal computers, workstations and the like, techniques forcompressing instruction codes have been proposed and brought intopractical use for reducing the capacity of program memories.

[0008] The compression techniques proposed for general-purposeinformation processing apparatuses, however, are not always suitable forapplications in built-in devices such as a micro-controller withoutmodification because these techniques are implemented, for example, onthe assumption that a cache has a relatively high hit rate, for purposesof improving the throughput of instructions, and the like. Specifically,built-in devices such as a micro-controller generally present cache hitrates not so high, and require a high responsibility to interrupts.Also, the built-in devices often regard the latency more important thanthe throughput of instructions. Further, the built-in devices arecharacterized by a high proportion of instruction codes (instructioncodes in a narrow sense excluding read data) included in programs.Therefore, what is important for the built-in devices is to expandcompressed codes to instruction codes faster than general-purposeinformation processing apparatuses.

SUMMARY OF THE INVENTION

[0009] It is an object of the present invention to provide instructioncode compressing technique which offers a high compression ratio and afast instruction expendability.

[0010] To achieve the above object, the present invention provides amicro-controller for performing a process in accordance with a program,which includes a dictionary memory for storing instruction codes whichappear in the program, and a compressed code memory for storingcompressed codes each converted from each of the instruction codesincluded in the program, wherein each compressed code has a word lengthsufficiently long to identify all instruction codes included in theprogram, and has a value indicative of an address in the dictionarymemory at which an associated instruction code is stored.

[0011] The micro-controller is responsive to an instruction code readrequest which specifies an address of a compressed code to read thecompressed code stored in the specified address in the compressed codememory, and to subsequently read an instruction code stored in anaddress indicated by the compressed code in the dictionary memory.

[0012] Each of instruction codes appearing in a program is converted toa compressed code having a number of bits required for identification.The dictionary memory for use in expanding the compressed code to anoriginal instruction code is stored in a program memory. The compressedcode is configured to indicate an address in the dictionary, therebyachieving the compression of instruction codes which offers a highcompression ratio and fast instruction expandability.

[0013] Other objects, features and advantages of the invention willbecome apparent from the following description of the embodiments of theinvention taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a block diagram for explaining a main portion in theconfiguration of one embodiment of a micro-controller according to thepresent invention;

[0015]FIG. 2A is a schematic diagram for explaining a relationshipbetween a compressed code memory and a dictionary memory provided in aprogram memory in a first embodiment which shows basic principles of thepresent invention;

[0016]FIG. 2B is a schematic diagram for explaining a conventionalprogram memory which does not use compressed codes;

[0017]FIG. 3 is a block diagram for explaining an exemplaryconfiguration of a program memory in a second embodiment;

[0018]FIG. 4 is a block diagram for explaining an exemplaryconfiguration of a program memory in a third embodiment;

[0019]FIG. 5 is a block diagram for explaining an exemplaryconfiguration of a program memory in a fourth embodiment;

[0020]FIG. 6 is a block diagram for explaining an exemplaryconfiguration of a program memory in a fifth embodiment;

[0021]FIG. 7 is a block diagram for explaining an exemplaryconfiguration of a program memory in a sixth embodiment;

[0022]FIG. 8 is a block diagram for explaining an exemplaryconfiguration of a program memory in a seventh embodiment;

[0023]FIG. 9 is a block diagram for explaining an exemplaryconfiguration of a program memory in an eighth embodiment;

[0024]FIG. 10 is a block diagram for explaining an exemplaryconfiguration of a program memory in a ninth embodiment;

[0025]FIG. 11 is a block diagram for explaining an exemplaryconfiguration of a program memory in a tenth embodiment;

[0026]FIG. 12 is a block diagram for explaining an exemplaryconfiguration of a program memory in an eleventh embodiment;

[0027]FIG. 13 is a block diagram for explaining an exemplaryconfiguration of a program memory in a twelfth embodiment;

[0028]FIG. 14A is a diagram for explaining an exemplary method oforganizing a compressed code memory and a dictionary memory in thetwelfth embodiment;

[0029]FIG. 14B is a diagram for explaining an exemplary modification tothe twelfth embodiment;

[0030]FIG. 15 is a block diagram for explaining an exemplaryconfiguration of a program memory in a thirteenth embodiment; and

[0031]FIG. 16 is a block diagram illustrating an exemplary apparatuswhich utilizes a micro-controller to which the present invention isapplied.

DESCRIPTION OF THE EMBODIMENTS

[0032] A variety of embodiments of the present invention will bedescribed below with reference to the accompanying drawings.

[0033]FIG. 1 is a block diagram for explaining the configuration of amain portion in one embodiment of a micro-controller to which thepresent invention is applied.

[0034] In FIG. 1, the micro-controller 10 comprises a CPU 20 forexecuting a program; a program memory 30 for storing programs, a RAM 40for temporarily storing a program, data and the like; a bus controller50 for controlling an external bus 65 and the like; and a CPU bus 60 forinterconnecting these components.

[0035] The CPU 20 is provided therein with a program counter 21 forcontrolling an order in which instructions in a program are executed.The program counter 21 indicates an address in the program memory 30which stores an instruction code to be next executed.

[0036] The bus controller 50 is connected to an external memory 90 andthe like, for example, through the external bus 65. The bus controller50 is also connected to a group of devices required for a particularapplication of the micro-controller, for example, a peripheral modulefor controlling an input device, a display device and the like, a DMAdevice, and the like through a peripheral module bus or the like.

[0037] The program memory 30 includes a compressed code memory 31; adictionary memory 32; and a controller 35 for controlling a read fromthe program memory 30. The controller 35 may be provided independently,for example, outside the program memory 30, or provided within the buscontroller 50. Also, the compressed code memory 31 and dictionary memory32 are preferably configured as separate memories such that they can besimultaneously read.

[0038]FIG. 2A is a schematic diagram for explaining a relationshipbetween the compressed code memory 31 and dictionary memory 32 providedin the program memory 30 in a first embodiment of the present inventionfor showing basic principles of the present invention.

[0039] Now, the compressed code memory 31 and dictionary memory 32 shownin FIG. 2A will be explained with reference to a schematic diagram forexplaining a conventional program memory, shown in FIG. 2B, which doesnot employ compressed codes.

[0040] In this embodiment, a compressed code is converted from aninstruction code (including a data portion) appearing in a program to acompressed code which has a shorter code length than the original codelength. All instruction codes appearing in a program are to becompressed. Therefore, a compression ratio can be improved. Originalinstruction codes are stored in the dictionary memory 32 for expandingcompressed codes.

[0041] Assuming, for example, that a program includes X lines oforiginal instruction codes each having a word length of n bits, as shownin FIG. 2B. Assume also that in this event, the number of types K ofinstruction codes appearing in the program is in a range of 2^(m−1) to2^(m). Generally, since the same instruction code often appears aplurality of times in a program, the number of types K of instructioncodes is smaller than X.

[0042] In this event, m bits are sufficient for identifying aninstruction code on each line of the program. Therefore, a sequence ofinstruction codes each having n bits on X lines (n bits×X lines) can beconverted to a sequence of compressed codes each having m bits on Xlines (m bits×X lines). Then, a dictionary having a capacity of n bits×K(K≦2^(m)) may be provided for expanding compressed codes to originalinstruction codes.

[0043] Assume further in this embodiment that an m-bit compressed codeis corresponded to a code indicative of the address of an instructioncode which should be referenced in the dictionary memory. In thismanner, an address in the dictionary memory can be directly found froman associated compressed code, so that a shorter time is required forexpanding the compressed code to an original instruction code withoutthe need for a complicated address conversion and the like.

[0044] Specifically, in the embodiment shown in FIG. 2A, as aninstruction address 61 is inputted to the program memory 30 inaccordance with the program counter 21, a compressed code (dictionarymemory address) is first read, and subsequently, an instruction code 62stored at this dictionary memory address is read. The program memory 30is controlled by the control unit 35 for reading the compressed code andinstruction code stored therein.

[0045] As is apparent from the foregoing explanation, the effect of codecompression in this embodiment depends on the type of instruction codewhich appears in a program.

[0046] Consider, for example, that a 1 Mbyte program includes 256K linesof instruction codes each having a 32-bit length. Assuming that 64K(=2¹⁶) types of instruction codes, which are equivalent to one quarterof the whole number of instruction codes, appear in the program, theinstruction codes can be compressed to compressed codes having a 16-bitlength.

[0047] In this event, the compressed code memory 31 requires thecapacity of 512 Kbytes (16 bits×256 K). Then, the dictionary memory 32requires the capacity of 256 Kbytes (32 bits×62 K). As a result, a totalcapacity of the compressed code memory 31 and dictionary memory 32amount to 768 Kbytes which is a reduction to 75% of 1 Mbyte which wouldbe required when the instruction codes are not compressed.

[0048] Assuming in another case that 32 K (=2¹⁵) types of instructioncodes, which are equivalent to one eighth of the whole number ofinstruction codes, appear in a program, a total capacity of thecompressed code memory 31 and dictionary memory 32 amount to 600 Kbyteswhich is a reduction to 59% of 1 Mbyte which would be required when theinstruction codes are not compressed.

[0049] On the other hand, assuming that a 1 Mbyte program includes 256K(=2¹⁸) lines of instruction codes each having a 32-bit length, all ofwhich are different from one another, the instruction codes arecompressed to compressed code having a 18-bit length.

[0050] In this event, the compressed code memory 31 requires thecapacity of 576 Kbytes (18 bits×256 K), while the dictionary memory 32requires the capacity of 1 Mbyte (32 bits×256 K). As a result, a totalcapacity of the compressed code memory 31 and dictionary memory 32amount to 1.6 Mbits which is 1.6 times larger than 1 Mbyte that isrequired when the instruction codes are not compressed.

[0051] Since an actual program has the nature of repeatedly using thesame instruction codes a plurality of times, types of appearinginstruction codes are in most cases reduced to approximately one fifthof the number of instruction codes. It is desired however that theprogram memory 30 can support even if the types of instruction codescannot be limited within a range in which the memory capacity can beeffectively reduced.

[0052] For the reason set forth above, in a second embodiment, theprogram memory 30 can be selectively utilized as the compressed codememory 31 and dictionary memory 32 as shown in FIG. 2A, and as a programmemory for storing instruction codes in a conventional format as shownin FIG. 2B. The second embodiment will be explained below with referenceto FIG. 3.

[0053]FIG. 3 is a schematic diagram for explaining an exemplaryconfiguration of the program memory 30 in the second embodiment. Here,the explanation will be given of a 32-bit instruction code and a 16-bitcompressed code, as an example, for simplicity. Of course, the presentinvention is not limited to these particular code lengths.

[0054] In the second embodiment, a compressed code memory 31 a can storeeither instruction codes or compressed codes. The compressed code memory31 a is not scheduled to store a mixture of instruction codes andcompressed codes.

[0055] The program memory 30 can be switched by a selector 81 a, aselector 81 b and a selector 81 c when it is utilized as a compressedcode memory 31 a and a dictionary memory 32 a and when it is utilized asa program memory for storing instruction codes in a conventional format.

[0056] When the program memory 30 is utilized for storing instructioncodes in a conventional format, the compressed code memory 31 a anddictionary memory 32 a are handled as a single continuous memory spacefor storing 32-bit instruction codes, and a stored instruction code 62 ais read from an address indicated by an instruction address 61 a.

[0057] In this event, since an instruction code has a 32-bit length, theinstruction address 61 indicated by the program counter 21 is a multipleof four (0, 4, 8, . . . ). A code b0, a code b1, and a code c0 in thefigure are 32-bit instruction codes, respectively.

[0058] When the program memory 30 is utilized for storing compressedcodes, the compressed code memory 31 a stores 16-bit compressed codes,and the dictionary memory 32 a stores 32-bit instruction codes forexpanding the compressed codes.

[0059] In this event, a code b0 and a code b1 in the figure are acombination of two consecutive 16-bit compressed codes. It is thereforenecessary to separately read former 16 bits and latter 16 bits whencompressed codes are read.

[0060] To meet this requirement, a shifter 85 is used in the exampleillustrated in FIG. 3, for using an instruction address 61 a which isshifted one bit to the lower digits. In this event, addresses in thecompressed code memory 31 a for 4-byte instruction addresses 0, 4, 8, 12are 0, 2, 4, 6, . . . Since the compressed code memory 31 a has a 32-bitwidth but ignores the two least significant bits of an address, the same32-bit data of an instruction address is read twice such as 0, 0, 4, 4,. . . Then, the selector 81 a uses the second least significant bit ofan address outputted from the shifter 85 to select an appropriatecompressed code from two compressed codes included in the output fromthe compressed code memory 31 a.

[0061] The selector 81 b is switched such that the instruction address61 a is inputted to the dictionary memory 32 a when the program memory30 is utilized for storing instruction codes in a conventional format.For storing compressed codes, the selector 81 b is switched such that acompressed code outputted from the selector 81 a is inputted to thedictionary memory 32 a. The selector 81 b may be switched, for example,using a memory mode signal 320 indicative of the contents of a registerwhich stores a storage format. The selector 81 c is responsive to theinstruction address 61 a to switch the outputs from the compressed codememory 31 a and dictionary memory 32 a to deliver an instruction code 62a when the program memory 30 is utilized for storing instruction codesin a conventional format. For storing compressed codes, the output fromthe dictionary memory 32 a is outputted as the instruction code 62 a atall times.

[0062] By thus configuring the program memory 30, even one and the samemicro-controller 10 can support the storage of instruction codes in aconventional format, and the storage of compressed codes by changingprograms stored therein. In other words, the micro-controller 10 towhich the present invention is applied can be utilized for generalpurposes.

[0063] Next, a third embodiment of the present invention will bedescribed with reference to FIG. 4 which is a block diagram forexplaining an exemplary configuration of a program memory 30 in thethird embodiment.

[0064] In the third embodiment, an original instruction code is dividedinto an operation field and an operand field which are separatelyencoded into compressed codes.

[0065] In FIG. 4, a compressed code memory 31 b stores m-bit compressedcodes. Here, the operation field of an instruction code indicates thetype of instruction such as calculation, memory access, branch or thelike, and the operand field of the instruction indicates a registernumber, data or the like.

[0066] Similarly, a dictionary memory is also comprised of an operationcode dictionary memory C32 b for expanding operation codes, and anoperand dictionary memory R33 b for expanding operands.

[0067] A compressed code 71 read from the compressed code memory 31 b isseparated into an operation code compressed code 71 c and an operandcompressed code 71 d. Then, the operation code dictionary memory C32 bis read with an address indicated by the operation code compressed code71 c, and the operand dictionary memory R33 b is read with an addressindicated by the operand compressed code 71 d. Subsequently, the codesread from the two dictionary memories in parallel are combined andoutputted as an instruction code 62 b.

[0068] By doing so, the capacity of the program memory can be furtherreduced in a program which is characterized by a particular operationcode or operand which appears highly frequently. In addition, since theoperation code and operand are expanded in parallel, an instruction codecan be read faster.

[0069] Next, a fourth embodiment of the present invention will beexplained with reference to FIG. 5 which is a block diagram forexplaining an exemplary configuration of a program memory 30 in thefourth embodiment.

[0070] In the fourth embodiment, an original instruction code is dividedinto an instruction code potion in a narrow sense, and a data portion,each of which is converted to a compressed code independently of eachother.

[0071] In FIG. 5, a compressed code memory 31 c stores m-bit compressedcodes. A compressed code includes a code indicative of a compressedinstruction code, and a code indicative of compressed data. It can bedetermined whether a read compressed code corresponds to an instructioncode or to data, for example, based on a timing at which the compressedcode is read, a reading mechanism, and the like.

[0072] Specifically, when a code is read at a timing of an instructionfetch stage in an execution cycle of the CPU 20, the read code can bedetermined to be a compressed instruction code, and when a code is readat a timing of a memory access stage, the read code can be determined tobe compressed data.

[0073] Then, a compressed code read as an instruction code is expandedwith reference to an instruction code dictionary memory I32 c, while acompressed code read as data is expanded with reference to a datadictionary memory D33 c.

[0074] In the fourth embodiment, since a compressed instruction code anda compressed data code can be distinguished upon reading, an independentcoding scheme can be provided for each of them. In other words, the samecode can be assigned to a compressed instruction code and to acompressed data code. It is therefore possible to reduce the bit widthof compressed codes stored in the compressed code memory 31 c.

[0075] Next, a fifth embodiment of the present invention will bedescribed with reference to FIG. 6 which is a block diagram forexplaining an exemplary configuration of a program memory 30 in thefifth embodiment.

[0076] In the fifth embodiment, a compressed code is also stored in anexternal memory 90 in addition to a compressed code memory 31 d. Thismay be applied to a program which has too large a capacity to be storedin the program memory 30.

[0077] In the example illustrated in FIG. 6, a compressed code from theexternal memory 90 is inputted into the program memory 30 through a buscontroller 50. Then, either a compressed code from the compressed codememory 31 d or the compressed code from the external code 90 is selectedby controlling a selector 81 d by a signal 341 from a controller 35.Then, an instruction code 62 d is outputted from an address in adictionary memory 32 d indicated by the selected compressed code.

[0078] Next, a sixth embodiment of the present invention will bedescribed with reference to FIG. 7 which is a block diagram forexplaining an exemplary configuration of a program memory 30 in thesixth embodiment.

[0079] In the sixth embodiment, a plurality of consecutive instructioncodes are collectively converted to a compressed code. For example, aset of three consecutive instructions are converted to a singlecompressed code which is stored in the fist one of three consecutivecodes within a compressed code memory 31 e. Then, the two subsequentcodes (called the “slots”) are skipped in execution to reduce powerconsumption caused by a memory access. An address in the dictionarymemory referenced in the slot is generated from the compressed codewhich has been first stored.

[0080] For purposes of description, FIG. 7 shows an example in whichsets of one instruction, two consecutive instructions, and threeconsecutive instructions are converted to compressed codes,respectively. Of course, the present invention is not limited to thesesets.

[0081] In the sixth embodiment, a dictionary memory 32 e is divided intoa one-instruction storage region, a two-instruction storage region, anda three-instruction storage region, each of which stores a dictionary(instruction codes) for sets of consecutive instructions of the numbercorresponding thereto. Then, an address sa0 indicative of a boundarybetween the one-instruction storage region and the two-instructionstorage region is stored in a register 721, and an address sa1indicative of a boundary between the two-instruction storage region andthe three-instruction storage region is stored in a register 722. Inthis manner, when the dictionary memory 32 e is referenced, it can bedetermined whether the address belongs to the one-instruction storageregion or the two-instruction storage region or the three-instructionstorage region.

[0082] For example, assume that a set of three consecutive instructionsc0, c1, c2 are collectively converted to a compressed code p0. In thisevent, a compressed code memory 31 e stores codes p0, slot 1, slot 2 insequence. The slot 1 and slot 2 are dummy data having the same bitlength as a compressed code. Then, the instruction c0 is stored in anaddress indicated by sa1 in the dictionary memory 32 e, and theinstructions c1, c2 are stored in sequence. Here, the address indicatedby p0 is included in the three-instruction storage region.

[0083] Assuming that the code p0 in the compressed code memory 31 e isspecified by an instruction address 61 e. A controller 35 e candetermine that p0 is included in the three-instruction storage region byreferencing the register 722.

[0084] The controller 35 e first outputs the instruction c0 stored inthe address indicated by sa1 in the dictionary memory 32 e as aninstruction code 62 e. Next, without referencing the compressed codememory 31 e, the controller 35 e calculates the address of aninstruction code subsequent to the instruction c0 in the dictionarymemory 32 e, and outputs the instruction c1 stored in that address asthe instruction code 62 e. Then, the subsequent c2 is outputted as theinstruction code 62 e in a similar manner. Subsequently, the controller35 e reads a compressed code subsequent to the slot 2 in the compressedcode memory 31 e. Of course, if an address indicated by a compressedcode belongs to the two-instruction storage region in the dictionarymemory 32 e, the processing for outputting instruction codes iscompleted when it is executed only once, without accessing thecompressed code memory 31 e.

[0085] In this manner, the grouping of instruction codes into a seteliminates the need for reading second and subsequent compressed codesin a plurality of compressed codes which are executed in sequence. Thus,the compressed code memory 31 e can be accessed a less number of times,thereby reducing power consumption caused by memory accesses.

[0086] Alternatively, a compressed code indicative of the address ofdata referenced in execution of an associated instruction code may bestored in a slot, rather than the dummy data. In this case, thecompressed code memory 31 e can be further effectively utilized.

[0087] Next, a seventh embodiment of the present invention will bedescribed with reference to FIG. 8 which is a block diagram forexplaining an exemplary configuration of a program memory 30 in theseventh embodiment.

[0088] The seventh embodiment is a modification to the aforementionedsixth embodiment.

[0089] In the seventh embodiment, a dictionary memory 32 f is dividedinto a one-instruction storage region and a consecutive-instructionstorage region. Then, an address sa indicative of a boundary between theone-instruction storage region and the consecutive-instruction storageregion is stored in a register 821.

[0090] When a compressed code corresponding to consecutive instructionsis stored in the compressed code memory 31 f, the number of consecutiveinstructions is stored in a slot 1.

[0091] Upon reading a compressed code, a controller 35 f can determinesby referencing the register 821 whether the compressed code correspondsto a single instruction or consecutive instructions. Then, when thecompressed code corresponds to a single instruction, the controller 35 freads an instruction code from the dictionary memory 32 f, and reads thenext compressed code from the compressed code memory 31 f. On the otherhand, when the compressed code corresponds to consecutive instructions,the controller 35 f reads an instruction code from the dictionary memory32 f, and then reads the next slot 1 to acquire the number ofconsecutive instructions. In accordance with the acquired number ofconsecutive instructions, the controller 35 f reads instruction codesfrom the dictionary memory 32 f without accessing the compressed codememory 31 f.

[0092] In the seventh embodiment, the power consumption can be reducedbecause the compressed code memory 31 f need not be read for third andsubsequent instructions in consecutive instructions. Also, like thesixth embodiment, compressed data codes may be stored in the slot 2onward.

[0093] Next, an eighth embodiment of the present invention will bedescribed with reference to FIG. 9 which is a block diagram forexplaining an exemplary configuration of a program memory 30 in theeighth embodiment.

[0094] In the eighth embodiment, a compressed code register 910 isprovided between a compressed code memory 31 g and a dictionary memory32 g. Compressed codes read from the compressed code memory 31 g duringone clock is stored in the compressed code register 910.

[0095] By doing so, the compressed code reading process and theexpansion to an instruction code by the dictionary memory 32 g can bedivided into two stages in a pipeline, thereby making it possible toreadily increase a clock frequency of the micro-controller 10.

[0096] Next, a ninth embodiment of the present invention will bedescribed with reference to FIG. 10 which is a block diagram forexplaining an exemplary configuration of a program memory 30 in theninth embodiment.

[0097] In the ninth embodiment, a dictionary register 1020 whichfunctions as a fast dictionary memory, a dictionary determining circuit1030, and a selector 1040 are added to the configuration of the eighthembodiment.

[0098] The dictionary register 1020 preferably stores an instructioncode which is frequently used, for example, an instruction code at abranched destination, or the like.

[0099] The dictionary determining circuit 1030 determines whether acompressed code read from a compressed code memory 31 h is expanded bythe dictionary register 1020 or by a dictionary memory 32 h. Theselector 1040 selects either the dictionary register 1020 or thedictionary memory 32 h based on a determination result of the dictionarydetermining circuit 1030, and outputs an instruction code 62 h.

[0100] By doing so, a frequently used instruction code, for example, aninstruction code at a branched destination can be expanded fast by usingthe dictionary register 1020. Particularly, the micro-controller 10 canbe prevented from degraded performance when a branch or the like occursto cause a discontinuous instruction address 61 h.

[0101] Next, a tenth embodiment of the present invention will beexplained with reference to FIG. 11 which is a block diagram forexplaining an exemplary configuration of a program memory 30 in thetenth embodiment.

[0102] In the tenth embodiment, two consecutive compressed codes areread simultaneously. In this event, the compressed codes are read atevery other clock. Also, a dictionary memory 32 is divided into adictionary memory A32 i and a dictionary memory B33 i, by way ofexample. Combinations of instruction codes stored in the two dictionarymemories are arbitrary. For example, instruction codes may bedistributed into two by the values of the most significant bits or leastsignificant bits. Alternatively, highly frequently used instructioncodes may be stored in both dictionary memories. Further alternatively,all instruction codes may be stored in both dictionary memories.

[0103] A controller 35 i stores two simultaneously read compressed codesin a register A1111 and a register B1112, respectively.

[0104] Then, when respective addresses indicated by the compressed codesstored in the register A1111 and register B1112 are stored in the twodifferent dictionary memories, instruction codes are read simultaneouslyfrom the two dictionary memories. On the other hands, when bothaddresses indicted by the compressed codes belong to one of the twodictionary memories, an instruction code indicated by the register A1111is first read, followed by reading an instruction code indicated by theregister B1112 in the next cycle.

[0105] When two instruction codes are read simultaneously, aninstruction code indicated by the register B1112 is stored in a register1120, and an instruction code indicated by the register A1111 isoutputted. Then, the instruction code indicated by the register B1112 isoutputted. On the other hand, when two instruction codes are read insequence, the instruction codes are outputted in the order in which theyare read.

[0106] In the event that a compressed code is read once in two cycles,if instruction codes are simultaneously read from the two dictionarymemories, the dictionary memories need not be accessed in the remainingone of the two cycles. This cycle can be utilized to read data from amemory, for example, thereby improving the performance of themicro-controller 10.

[0107] Next, an eleventh embodiment of the present invention will beexplained with reference to FIG. 12 which is a block diagram forexplaining an exemplary configuration of a program memory 30 in theeleventh embodiment.

[0108] In the eleventh embodiment, the dictionary register in theaforementioned ninth embodiment is added to the configuration of thetenth embodiment.

[0109] Like the tenth embodiment, in the eleventh embodiment, twoconsecutive compressed codes are read simultaneously. Then, it isdetermined whether or not the first compressed code can be expanded bythe dictionary register 1210. If it can be expanded by the dictionaryregister 1210, the compressed code is expanded to an instruction code inone cycle, and the second compressed code can be expanded in the nextcycle using a dictionary memory A32 j or a dictionary memory B33 j.

[0110] If the first compressed code cannot be expanded in the dictionaryregister 1210, a process similar to that in the tenth embodiment isperformed to output consecutive instruction codes in order.

[0111] Next, a twelfth embodiment of the present invention will beexplained with reference to FIG. 13 which is a block diagram forexplaining an exemplary configuration of a program memory 30 in thetwelfth embodiment.

[0112] The twelfth embodiment takes as an example an originalinstruction which has a code length of 16 bits. In the presentinvention, it is contemplated that as an original instruction code isshorter, the compression ratio is lower. For this reason, in the twelfthembodiment, two 16-bit instruction codes are grouped into a set which isconverted to a single compressed code. In the example illustrated inFIG. 13, compressed codes each have a 16-bit length and are read one byone by an instruction address 61 k. A read compressed code is used as anaddress in a dictionary memory 32 k to simultaneously read 16-bitinstruction codes. By doing so, a high compression ratio can be achievedeven if the original instructions have a short code length.

[0113] An exemplary,method of organizing a compressed code memory 31 kand dictionary memory 32 k in this event will be explained withreference to FIGS. 14A, 14B.

[0114]FIG. 14A shows that a compressed code p0 indicates a combinationof instruction codes c0, c1. In a dictionary memory 32 j in FIG. 14A,16-bit instruction codes are combined as “c0, c0”, “c0, c1”, “c0, c2”,“c0, c3”. . .

[0115] With the foregoing combination, the capacity of the dictionarymemory 32 j can be reduced by organizing the compressed code memory 31 jand dictionary memory 32 j as shown in FIG. 14B.

[0116] Specifically, the dictionary memory 32 k stores instruction codesin combination of “c0, c1” and “c2, c3.” Then, a compressed code 1420 isdivided into an address portion 1421 indicative of the first instructioncode in a combination, and a difference portion 1422 (either of 0-3 inthis example) indicative of the second instruction code in thecombination, and the two portions are separately stored in thedictionary memory 32 k. For example, when the address portion 1421indicates “c0” and the difference portion 1422 indicates “2,” thiscompressed code represents a combination of instruction codes “c0, c2.”When the difference portion 1422 indicates “0,” the compressed codeindicates a combination of instruction codes “c0, c0.”

[0117] The foregoing exemplary configuration can be applied as well toan instruction code which has an arbitrary bit length.

[0118] Next, a thirteenth embodiment of the present invention will beexplained with reference to FIG. 15 which is a block diagram forexplaining an exemplary configuration of a program memory 30 in thethirteenth embodiment.

[0119] The thirteenth embodiment illustrates an exemplary configurationwhen a compressed code memory 311 and a dictionary memory 321 arephysically located on the same memory device 1500 so that they cannot beread simultaneously (the foregoing embodiments have been described onthe assumption that the compressed code memory can be readsimultaneously with the dictionary memory. However, they may be locatedon the same memory device).

[0120] In the thirteenth embodiment, a 16-bit compressed code p0 is readwith an instruction address 611, and held in a register 1510. Then, inthe next cycle after the compressed code was read, 16-bit instructioncodes c0, c1, for example, are simultaneously read based on an addressindicated by the compressed code held in the register 1510.

[0121] Even if the compressed code memory 311 and dictionary memory 321are physically located on the same memory device 1500, a compressed codeand an instruction code can be read simultaneously by using, forexample, a two-port memory from which a plurality of data can be read inparallel.

[0122]FIG. 16 is a block diagram of an apparatus which utilizes amicro-controller 100 to which the present invention is applied. In FIG.16, the micro-controller 100 comprises a direct memory access controller(DMA) 51; an interrupt controller (INT) 52, for example, a timer; acommunication interface; and a peripheral module 53 such as an A/Dconverter, all of which are connected to a bus controller 50.

[0123] External to the micro-controller 100, a group of external devices120 are connected through the bus controller 50, DMA 51, INT 52, and thelike. The external devices 120 may be, for example, a memory, a key, adisplay device, and the like depending on applications of themicro-controller 100. Such an apparatus can be applied to an ECU(Electronic Control Unit), for example, in a system built in a car.

[0124] As described above, the present invention provides theinstruction code compression technique which offers a high compressionratio and fast instruction expandability.

[0125] It should be further understood by those skilled in the art thatthe foregoing description has been made on embodiments of the inventionand that various changes and modifications may be made in the inventionwithout departing from the spirit of the invention and the scope of theappended claims.

What is claimed is:
 1. A micro-controller for performing a process inaccordance with a program, comprising: two dictionary memories forstoring instruction codes which appear in the program; a compressed codememory for storing compressed codes each converted from each of theinstruction codes included in the program, each said compressed codehaving a word length sufficiently long to identify all instruction codesincluded in the program, each said compressed code having a valueindicative of an address in said dictionary memory at which anassociated instruction code is stored; and reading means forsimultaneously reading two consecutive compressed codes every otherclock and temporarily storing the two compressed codes in registers,respectively, responsive to an instruction code read request whichspecifies an address of a compressed code, to read two consecutivecompressed codes stored in the specified address in said compressed codememory, and to store the read compressed codes in said registers,responsive to the compressed codes which respectively indicate differentdictionary memories to simultaneously read instruction codes stored ataddresses indicated by the respective compressed codes, and to outputthe instruction codes in an order of the consecutive compressed codesassociated therewith, and responsive to the compressed codes whichrespectively indicate the same dictionary memory to read instructioncodes stored at addresses indicated by the compressed codes in an orderof the consecutive compressed codes, and to output the instructioncodes.
 2. A micro-controller for performing a process in accordance witha program, comprising: a dictionary register for storing a predeterminedparticular instruction code out of instruction codes which appear in theprogram; two dictionary memories for storing the instruction codes otherthan said particular instruction code out of the instruction codes whichappear in the program; a compressed code memory for storing compressedcodes each converted from each of the instruction codes included in theprogram, each said compressed code having a word length sufficientlylong to identify all instruction codes included in the program, eachsaid compressed code having a value indicative of addresses in saiddictionary memories at which associated instruction codes are stored oran address in said dictionary register at which one of the associatedinstruction codes is stored; and reading means for simultaneouslyreading two consecutive compressed codes every other clock andtemporarily storing the two compressed codes in registers, respectively,wherein responsive to an instruction code read request which specifiesan address of a compressed code, to read two consecutive compressedcodes stored in the specified address in said compressed code memory,responsive to the first one of the two consecutive compressed code whichindicates said dictionary register to read and output an instructioncode stored at an address indicated by the first compressed code, and tosubsequently read and output an instruction code stored in saiddictionary memory or in a register in said dictionary register indicatedby the second compressed code, responsive to the first one of the twoconsecutive compressed code which does not indicate said dictionaryregister to determine whether or not the respective compressed codesindicate different dictionary memories, simultaneously to readinstruction codes stored at addresses indicated by the respectivecompressed codes, and output the instruction codes in an order of theconsecutive compressed codes associated therewith, when the respectivecompressed codes indicate different dictionary memories, and to read andoutput instruction codes stored at addresses indicated by the compressedcodes in an order of the consecutive compressed codes when therespective compressed codes indicates the same dictionary memory.
 3. Amicro-controller according to claim 2, wherein: said dictionary registeris capable of reading an instruction code faster than said dictionarymemory, and said dictionary register stores at least one instructioncode at a branch destination of an instruction code which instructs abranch.
 4. A micro-controller for performing a process in accordancewith a program, comprising: a dictionary memory region for storinginstruction codes which appear in the program; and a compressed codememory for storing compressed codes each converted from a set of twoconsecutive instruction codes included in the program, each saidcompressed code memory having a word length sufficiently long toidentify all instruction code sets included in the program, each saidcompressed code having a value indicative of an address in saiddictionary memory in which the associated instruction code set isstored, responsive to an instruction code read request which specifiesan address of a compressed code, to read a compressed code stored in thespecified address in said compressed code memory, and to subsequentlyread an instruction code set stored in an address indicated by thecompressed code in said dictionary memory.
 5. A micro-controller forperforming a process in accordance with a program, comprising: a memoryincluding a dictionary memory region for storing instruction codes whichappear in the program, and a compressed code memory region for storingcompressed codes each converted from each of the instruction codesincluded in the program, each said compressed code having a word lengthsufficiently long to identify all instruction codes included in theprogram, each said compressed code having a value indicative of anaddress in said dictionary memory at which an associated instructioncode is stored; and a register for temporarily storing a read compressedcode, wherein responsive to an instruction code read request whichspecifies an address of a compressed code, to read a compressed codestored at the specified address in said compressed code memory region,to store the compressed code in said register, and to read aninstruction code stored in an address in said dictionary memory regionindicated by the compressed code stored in said register.
 6. Amicro-controller according to claim 5, wherein: said memory comprises atwo-port memory capable of reading in parallel, wherein said compressedcode is read through a first port, and said instruction code is readfrom a second port.
 7. A micro-controller for performing a process inaccordance with a program, comprising: a dictionary memory for storinginstruction codes which appear in the program; and a compressed codememory for storing compressed codes each converted from a set of twoconsecutive instruction codes included in the program, each saidcompressed code memory having a word length sufficiently long toidentify respective first instruction codes in the instruction codesets, each said compressed code having a value comprised of a firstportion indicative of an address in said dictionary memory in which theassociated instruction code set is stored, and a second portionindicative of a position in said dictionary memory at which the secondinstruction code in said instruction code set is stored as a relativevalue to said address, wherein responsive to an instruction code readrequest which specifies an address of a compressed code, to read acompressed code stored at the specified address in said compressed codememory, to read an instruction code stored in the address indicated bythe first portion of said compressed code in said dictionary memory, andto read an instruction code identified by the second portion of saidcompressed code.
 8. An apparatus built in a car, comprising amicro-controller including: a dictionary memory for storing instructioncodes which appear in the program; and a compressed code memory forstoring compressed codes each converted from each of the instructioncodes included in the program, each said compressed code having a wordlength sufficiently long to identify all instruction codes included inthe program, each said compressed code having a value indicative of anaddress in said dictionary memory at which an associated instructioncode is stored, wherein responsive to an instruction code read requestwhich specifies an address of a compressed code, to read the compressedcode stored in the specified address in said compressed code memory, andto subsequently read an instruction code stored in an address indicatedby the compressed code in said dictionary memory.